1. Field of the Invention
As processors have gotten cheaper, more and more digital data processing systems have appeared in which several processors operate as coprocessors. A coprocessor is a processor which cooperates with another processor to process data. Classic examples of coprocessors are floating-point units for performing floating point arithmetic and I/O processors for handling the flow of data between peripheral devices such as terminals and the system memory. The relationship between two coprocessors lies along a continuum whose ends are described by the notions tightly coupled and loosely coupled. One coprocessor is tightly coupled to another when there is a high degree of direct interaction between the coprocessors. For example floating point units are typically tightly coupled. The processor served by the floating point unit provides the operands to the floating point unit, indicates the operation to be performed, and receives the results directly from the floating point unit. The results typically not only include the result value, but also signals indicating the status of the floating point operation. I/O processors, on the other hand, are typically loosely coupled. Communication with the processor they serve is generally through the system memory. When the processor requires the assistance of the I/O processor to output data, the processor places the output data and a description of what the I/O processor is to do with it in memory at a location known to the I/O processor and then indicates to the I/O processor that the data is in memory. The I/O processor thereupon responds to the indication by retrieving the data from memory and outputting it to the desired peripheral device. When it is finished, it puts a record of the status of the operation in memory at a location known to the processor and indicates to the processor that it has finished the memory operation. The processor then responds to the indication by reading the data at the location to determine the status of the output operation.
2. Description of the Prior Art
A coprocessor must deal with data as it is provided by the host processor. Since host processors may differ and even a given host processor has data of different sizes, the coprocessor must be able to easily process data of different sizes. Prior-art processors have tended to optimize towards one size (usually the same as the size of the processor's internal data bus) or at most to permit a given register to be used alternatively for one of a number of sizes. For example, the Motorola 680.times.0 architecture permits a general register to be used as a byte register, a 16-bit word register, or as a 32-bit pointer register. In one machine, the Intel 8051, there are certain special byte registers in which each bit may be addressed for Boolean operations. Two of the Boolean operations are moving an addressed bit to a single-bit CARRY register and moving the contents of the CARRY register to an addressed bit in one of the special byte registers.
While the Motorola approach permits processing of data of different sizes, it does so at considerable cost. There is first the waste of register space: if a register is being used as a byte register, the remaining three bytes are simply unavailable. Second, there is the difficulty of subdividing data; for example, when a register is being used as a word register, separate operations on the bytes of the word are not possible. Third, because data cannot be subdivided, it must be fetched from memory in the same units in which it is processed internally. For example, it is not possible to fetch a word and then process the bytes of the word individually. In the case of the Intel 8051, the design permits the special registers to be used for condition codes and the like, but does not aid in the processing of data of different sizes. It is an object of the present invention to provide apparatus in a processor which permits more efficient processing of different-sized data than has been heretofore possible.